USR-ES1 is embedded with Wiznet's W5500 chip, and uses hardware logic gate circuits to implement the transport layer and network layer of the TCP/IP protocol stack (such as: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE and other protocols), and integrates Data link layer, physical layer, and 32K bytes of on-chip RAM are used as data receiving and sending buffers. Make the host computer main control chip only need to undertake the processing task of TCP/IP application layer control information. This greatly saves the workload of the host computer on data replication, protocol processing, and interrupt processing, and improves system utilization and reliability.
During operation, users can use W5500 as a peripheral RAM of MCU, which is very simple. The external interface of W5500 is a general 80MHz high-speed SPI, which can be selected for different platforms to expand high-speed Ethernet solutions. Auto-negotiation LED status shows that the SPI interface is fast and stable.
The size and pins are compatible with Wiznet's official module WIZ820io
Features :
1. 80MHz high-speed SPI interface
2. Built-in hardware TCPIP protocol stack, users almost don't need to master the complexity
Knowledge of network protocols
3. Support up to 8 Socket connections
4. Support TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE protocol
5. Integrated data link layer and physical layer
6. Support wake up after power failure
7. Support high-speed serial peripheral interface (SPI mode 0~3)
8. Internal 32K bytes transmit and receive buffer
9. Embedded 1 OBaseT/10 OBaseTX Ethernet physical layer (PHY)
10. Support auto negotiation (10/100-Based full double earth/half double earth)
11. IP fragmentation is not supported
12. 3.3V working voltage, 5V withstand voltage of I/O signal port
13. LED status display (full duplex/half duplex, network connection, network speed, activity status
14. Ultra-small pin-type package, convenient for embedded applications
15. Provide C application routines
Product Parameters:
1. Power supply mode: 3.3V external power supply, current should be greater than 200mA
2. Control interface form: 3.3V TTL level, SPI interface, 2*single row pin
Pin Description:
GND: ground, power negative
VIN3.3: 3.3V power supply positive
PWDN: Pin is used for power down mode
High level: power-down mode enabled
Low level: Normal mode enabled
nREST: This pin is active low, used to reset and reinitialize W5500
MISO: SPI master input and slave output
MOSI: SPI master output and slave input
SCLK: SPI clock pin
nSS: SPI chip select pin, active low
nINT: interrupt pin, active low
The W5500 module is an Ethernet module based on the WIZNET main push model chip 5500. The module integrates the full hardware TCP/IP protocol stack, requires no code to implement the TCP/IP protocol stack, supports 10/100MBPS transmission rate, supports sleep mode and network call N. The internal integrated 32K TX/RX buffer supports 8 independent ports to run the module at the same time. It supports 3.3V or 5V power supply, which is convenient for users to use in different MCU systems. The communication mode between module and MCU system is SPI protocol, support up to 80M SPI clock frequency, providing program routines for STM32 and 51 MCU client, server, UDP three working modes
W5500 module pin header function description:
Product Size:
W5100, W5200, W5500 Parameter Comparison:
